Ghazi Abdulbaqia, Alaa and Hashim, Yasir (2022) Design and Implementation of General Hardware Binary Multiplier (2nx 2n) Bits. Journal of Physics: Conference Series.
Text (Research Article)
Abdulbaqia_2022_J._Phys.__Conf._Ser._2312_012084.pdf - Published Version Download (856kB) |
Abstract
In this paper, a new general 2n x 2n bits hardware multiplier based on combinatorial has been designed, implemented and analysed. First, a new design for circuit to multiply two binary numbers with 2n bits length, this new design starts with basic 2x2 bits circuit multiplier, n here equal to 1. Then based on this circuit, the 4x4 bits circuit multiplier has been designed. And based on 4x4, the 8x8 bits multiplier has been designed and continually the 16x16 bits multiplier. The final design for general 2nx2n bits multiplier has been presented. All these circuits have been mathematically proved and tested to get the final results.
Item Type: | Article |
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Subjects: | Engineering > Computer engineering |
Depositing User: | TIU ePrints Admin |
Date Deposited: | 18 Oct 2022 07:53 |
Last Modified: | 05 Dec 2022 07:56 |
URI: | http://eprints.tiu.edu.iq/id/eprint/1039 |
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